參數(shù)資料
型號: 74VHC125N
廠商: Fairchild Semiconductor
文件頁數(shù): 6/9頁
文件大?。?/td> 0K
描述: IC BUFF TRI-ST QD N-INV 14DIP
標準包裝: 25
系列: 74VHC
邏輯類型: 緩沖器/線路驅動器,非反相
元件數(shù): 4
每個元件的位元數(shù): 1
輸出電流高,低: 8mA,8mA
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 14-DIP(0.300",7.62mm)
供應商設備封裝: 14-DIP
包裝: 管件
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC125 Rev. 1.4.0
6
74VHC125
Quad
Buff
er
with
3-ST
A
TE
Outputs
Physical Dimensions
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specications do not expand the terms of Fairchild’s worldwide terms and conditions,
specically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8
°
0
°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45
°
1
0.10
C
B
C
A
7
M
14
B
A
8
SEE DETAIL A
5.60
0.65
1.70
1.27
8.75
8.50
7.62
6.00
4.00
3.80
(0.33)
1.27
0.51
0.35
1.75 MAX
1.50
1.25
0.25
0.10
0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
0.50
0.25
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