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參數(shù)資料
| 型號： | 74VCX163245MTDX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs |
| 中文描述： | ALVC/VCX/A SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, MO-153ED, TSSOP-48 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 342K |
| 代理商： | 74VCX163245MTDX |
74VCX163245
8/15
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device
switching in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|
2) Parameter guaranteed by design
CAPACITANCE CHARACTERISTICS
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per circuit)
Symbol
Parameter
Test Condition T
A
= -40 to 85 °C
Unit
V
CCB
= 1.8
±
0.15V V
CCB
= 1.8
±
0.15V
V
CCB
= 2.5
±
0.2V
V
CCA
= 2.5
±
0.2V
V
CCA
= 3.3
±
0.3V
V
CCA
= 3.3
±
0.3V
Min.
Max.
Min.
Max.
Min.
Max.
t
PLH
, t
PHL
Propagation Delay Time An to Bn
t
PLH
, t
PHL
Propagation Delay Time Bn to An
t
PZL
, t
PZH
Output Enable Time OE to An
t
PZL
, t
PZH
Output Enable Time OE to Bn
t
PLZ
, t
PHZ
Output Disable Time OE to An
t
PLZ
, t
PHZ
Output Disable Time OE to Bn
t
OSLH
t
OSHL
1.0
1.0
1.0
1.0
1.0
1.0
5.8
5.5
5.3
8.3
5.2
4.6
5.0
1.0
1.0
1.0
1.0
1.0
1.0
6.2
5.1
5.1
8.2
5.6
4.5
0.5
1.0
1.0
1.0
1.0
1.0
1.0
4.4
4.0
4.0
4.6
4.8
4.4
0.75
ns
ns
ns
Output To Output Skew Time
(note1, 2)
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CCB
(V)
V
CCA
(V)
T
A
= 25 °C
-40 to 85 °C
Min.
Typ.
Max.
Min.
Max.
C
INA
C
I/O
Input Capacitance
Input/Output
Capacitance
Power Dissipation
Capacitance
open
2.5
open
3.3
5
6
V
V
C
PD
2.5
3.3
f=10MHz
20
V
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