參數(shù)資料
型號: 74VCX163245MTDX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
中文描述: ALVC/VCX/A SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48
封裝: 6.10 MM, MO-153ED, TSSOP-48
文件頁數(shù): 1/15頁
文件大?。?/td> 342K
代理商: 74VCX163245MTDX
1/15
June 2003
I
HIGH SPEED: t
PD
= 4.4ns (MAX.) at T
A
=85°C
V
CCA
= 3.0V V
CCB
= 2.3V
LOW POWER DISSIPATION:
I
CCA
= I
CCB
= 20
μ
A(MAX.) at T
A
=85°C
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OHA
| = I
OLA
= 12mA MIN at
V
CCA
= 3.0V V
CCB
= 1.65V or 2.3V
|I
OHA
| = I
OLA
= 8mA MIN at
V
CCA
= 2.3V V
CCB
= 1.65V)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
OPERATING VOLTAGE RANGE:
V
CCA
(OPR)=2.3Vto3.6V(1.2VDataRetention)
V
CCB
(OPR)=1.65Vto2.7V(1.2VDataRetention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16245
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
I
I
I
I
I
I
I
I
DESCRIPTION
The 74VCX163245 is a dual supply low voltage
CMOS 16-BIT BUS TRANSCEIVER fabricated
with sub-micron silicon gate and five-layer metal
wiring C
2
MOS technology. Designed for use as an
interface between a 3.3V bus and a 2.5V or 1.8V
bus in a mixed 3.3V/1.8V,3.3V/2.5V and 2.5V/
1.8V supply systems, it achieves high speed
operation while maintaining the CMOS low power
dissipation.
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
nDIR inputs. The enable inputs nOE can be used
to disable the device so that the buses are
effectively isolated. The A-port interfaces with the
3V bus, the B-port with the 2.5V and 1.8V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD im-
munity and transient excess voltage. All floating
bus terminals during High Z State must be held
HIGH or LOW.
74VCX163245
16-BIT DUAL SUPPLY BUS TRANSCEIVER
LEVEL TRANSLATOR
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
ORDER CODES
PACKAGE
TRAY
T & R
TSSOP48
TFBGA54
μ
TFBGA42
74VCX163245TTR
74VCX163245LBR
74VCX163245TBR
74VCX163245LB
74VCX163245TB
TSSOP
μ
TFBGA
TFBGA
TARGET DATA
LOGIC DIAGRAM
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