參數(shù)資料
型號: 74VCX163245MTD
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
中文描述: ALVC/VCX/A SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48
封裝: 6.10 MM, MO-153ED, TSSOP-48
文件頁數(shù): 7/15頁
文件大小: 342K
代理商: 74VCX163245MTD
74VCX163245
7/15
DYNAMIC SWITCHING CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Value
Unit
V
CCB
(V)
V
CCA
(V)
T
A
= 25 °C
-40 to 85 °C
Min.
Typ.
Max.
Min.
Max.
V
OLPA
Dynamic Low Level
Quiet An Output
1.8
1.8
2.5
1.8
1.8
2.5
1.8
1.8
2.5
1.8
1.8
2.5
1.8
1.8
2.5
1.8
1.8
2.5
2.5
3.3
3.3
2.5
3.3
3.3
2.5
3.3
3.3
2.5
3.3
3.3
2.5
3.3
3.3
2.5
3.3
3.3
C
L
=30pF
V
IL
=0V V
IH
=Vcc
0.25
0.25
0.6
0.6
0.8
0.8
-0.6
-0.8
-0.8
-0.25
-0.25
-0.6
1.7
2.0
2.0
1.3
1.3
1.7
V
V
OLPB
Dynamic Low Level
Quiet Bn Output
C
L
=30pF
V
IL
=0V V
IH
=Vcc
V
V
OLVA
Dynamic Low Level
Quiet An Output
C
L
=30pF
V
IL
=0V V
IH
=Vcc
V
V
OLVB
Dynamic Low Level
Quiet Bn Output
C
L
=30pF
V
IL
=0V V
IH
=Vcc
V
V
OHVA
Dynamic Low Level
Quiet An Output
C
L
=30pF
V
IL
=0V V
IH
=Vcc
V
V
OHVB
Dynamic Low Level
Quiet Bn Output
C
L
=30pF
V
IL
=0V V
IH
=Vcc
V
Symbol
Parameter
Test Condition
Value
Unit
V
CCB
(V)
V
CCA
(V)
-40 to 85 °C
Min.
Max.
t
PLH
t
PHL
Propagation Delay Time
An to Bn
1.8
±
0.15
1.8
±
0.15
2.5
±
0.2
1.8
±
0.15
1.8
±
0.15
2.5
±
0.2
1.8
±
0.15
1.8
±
0.15
2.5
±
0.2
1.8
±
0.15
1.8
±
0.15
2.5
±
0.2
1.8
±
0.15
1.8
±
0.15
2.5
±
0.2
1.8
±
0.15
1.8
±
0.15
2.5
±
0.2
1.8
±
0.15
1.8
±
0.15
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
3.3
±
0.3
2.5
±
0.2
3.3
±
0.3
3.3
±
0.3
2.5
±
0.2
3.3
±
0.3
3.3
±
0.3
2.5
±
0.2
3.3
±
0.3
3.3
±
0.3
2.5
±
0.2
3.3
±
0.3
3.3
±
0.3
2.5
±
0.2
3.3
±
0.3
3.3
±
0.3
2.5
±
0.2
3.3
±
0.3
3.3
±
0.3
C
L
= 30 pF
R
L
= 500
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.8
6.2
4.4
5.5
5.1
4.0
5.3
5.1
4.0
8.3
8.2
4.6
5.2
5.6
4.5
4.6
4.5
4.4
0.5
0.5
0.75
ns
t
PLH
t
PHL
Propagation Delay Time
Bn to An
C
L
= 30 pF
R
L
= 500
ns
t
PZL
t
PZH
Output Enable Time
OE to An
C
L
= 30 pF
R
L
= 500
ns
t
PZL
t
PZH
Output Enable Time
OE to Bn
C
L
= 30 pF
R
L
= 500
ns
t
PLZ
t
PHZ
Output Disable Time
OE to An
C
L
= 30 pF
R
L
= 500
ns
t
PLZ
t
PHZ
Output Disable Time
OE to Bn
C
L
= 30 pF
R
L
= 500
ns
t
OSLH
t
OSHL
Output To Output Skew
Time (note1, 2)
C
L
= 30 pF
R
L
= 500
ns
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