參數(shù)資料
型號: 74V2G07STR
廠商: 意法半導(dǎo)體
英文描述: TRIPLE BUFFER (OPEN DRAIN)
中文描述: 三重緩沖(開漏)
文件頁數(shù): 1/9頁
文件大?。?/td> 199K
代理商: 74V2G07STR
1/9
November 2001
I
HIGH SPEED: t
PD
=3.7ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1
μ
A(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUT
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
DESCRIPTION
The 74V2G07 is an advanced high-speed CMOS
TRIPLE BUFFER (OPEN DRAIN) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on input and 0
to 7V can be accepted on input with no regard to
the supply voltage. This device can be used to
interface 5V to 3V.
74V2G07
TRIPLE BUFFER (OPEN DRAIN)
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
T & R
SOT23-8L
SOT323-8L
74V2G07STR
74V2G07CTR
SOT323-8L
SOT23-8L
PRELIMINARY DATA
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