參數(shù)資料
型號: 74V2G08STR
廠商: 意法半導(dǎo)體
英文描述: DUAL 2-INPUT AND GATE
中文描述: 雙2輸入與門
文件頁數(shù): 1/7頁
文件大小: 127K
代理商: 74V2G08STR
1/7
June 2003
I
HIGH SPEED: t
PD
= 3.8ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1
μ
A(MAX.) at T
A
= 25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
DESCRIPTION
The 74V2G08 is an advanced high-speed CMOS
DUAL
2-INPUT
AND
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
GATE
fabricated
with
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
74V2G08
DUAL 2-INPUT AND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
T & R
SOT23-8L
74V2G08STR
SOT23-8L
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