參數(shù)資料
型號: 74LVX3245MTC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
中文描述: LV/LV-A/LVX/H SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: 4.40 MM, MO-153AD, TSSOP-24
文件頁數(shù): 5/10頁
文件大?。?/td> 185K
代理商: 74LVX3245MTC
74LVX3245
5/10
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50pF, Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
3) Typical values at V
= 3.3V, V
CCB
= 5.0V
(*) Voltage range is 3.0V
±
0.3V
Symbol
Parameter
Test Condition
Value
(3)
Unit
V
CCA
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
Propagation Delay
Time (An to Bn)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
2.7
3.0
(*)
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
9.0
8.5
8.5
8.0
9.0
8.5
9.5
9.0
8.5
8.5
8.0
7.5
8.5
8.0
8.5
8.0
9.5
9.0
10.0
9.5
9.0
8.5
7.5
7.0
1.5
1.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
10.0
9.5
9.5
9.5
10.0
9.5
10.5
10.0
9.5
9.5
9.0
8.5
9.5
8.5
9.0
8.5
10.0
9.5
10.5
10.0
9.5
9.0
8.0
8.0
1.5
1.5
ns
1.0
5.4
8.0
t
PHL
Propagation Delay
Time (An to Bn)
1.0
5.6
7.5
t
PZL
Output Enable
Time (G to Bn)
ns
1.0
4.8
8.0
t
PZH
Output Enable
Time (G to Bn)
1.0
6.3
8.5
t
PLZ
Output Disable
Time (G to Bn)
ns
1.0
5.3
7.5
t
PHZ
Output Disable
Time (G to Bn)
1.0
4.2
7.0
t
PLH
Propagation Delay
Time (Bn to An)
ns
1.0
5.1
7.5
t
PHL
Propagation Delay
Time (Bn to An)
1.0
5.7
7.5
t
PZL
Output Enable
Time (G to An)
ns
1.0
6.3
8.5
t
PZH
Output Enable
Time (G to An)
1.0
6.8
9.0
t
PLZ
Output Disable
Time (G to An)
ns
1.0
5.3
8.0
t
PHZ
Output Disable
Time (G to An)
1.0
3.7
0.5
0.5
6.5
1.0
1.0
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
ns
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