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參數(shù)資料
| 型號(hào)： | 74LVX373MTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS |
| 中文描述： | 低電壓CMOS八進(jìn)制D型鎖存器（三態(tài)非刑事調(diào)查。容限為5V輸入） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 81K |
| 代理商： | 74LVX373MTR |
1/10
July 2001
I
HIGH SPEED:
t
PD
=5.8ns (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
=3V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25
°
C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
=3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
The 74LVX373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
PIN CONNECTION AND IEC LOGIC SYMBOLS
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the(OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All
inputs
and
outputs
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
are
equipped
with
74LVX373
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
TSSOP
74LVX373M
74LVX373MTR
74LVX373TTR
TSSOP
SOP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVX373TTR | LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS |
| 74LVX4245 | OCTAL DUAL SUPPLY BUS TRANSCEIVER |
| 74LVX4245MTR | OCTAL DUAL SUPPLY BUS TRANSCEIVER |
| 74LVX4245TTR | OCTAL DUAL SUPPLY BUS TRANSCEIVER |
| 74LVX4245 | 8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVX373MX | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVX373SJ | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVX373SJ_Q | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVX373SJX | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVX373TTR | 功能描述:閉鎖 Octal "D" Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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