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參數(shù)資料
| 型號(hào)： | 74LVTH16500 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
| 中文描述： | 低電壓18位通用總線收發(fā)器與三態(tài)輸出的初步 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 67K |
| 代理商： | 74LVTH16500 |
Preliminary
2000 Fairchild Semiconductor Corporation
DS012447
www.fairchildsemi.com
May 2000
Revised May 2000
7
74LVTH16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16500 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LVTH16500 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceiver is designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16500 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
I
Live insertion/extraction permitted
I
Power Up/Down high impedance provides glitch-free
bus loading
I
Outputs source/sink
32 mA/
+
64 mA
I
Functionally compatible with the 74 series 16500
I
Latch-up performance exceeds 500 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
Order Number
74LVTH16500MEA
74LVTH16500MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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PDF描述 |
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| 74LVTH16500MEA | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
| 74LVTH16500MTD | Octal Bus Transceivers With 3-State Outputs 20-PDIP -40 to 85 |
| 74LVTH16501 | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
| 74LVTH16501MEA | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
| 74LVTH16501MTD | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH16500 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVTH16500DGGRE4 | 功能描述:通用總線函數(shù) 3.3V ABT 18-Bit Univ Bus Trncvr W/3St Otp RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16500DGGRG4 | 功能描述:通用總線函數(shù) 3.3-V ABT 18B Univ Bus Xcvr RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16500DLRG4 | 功能描述:總線收發(fā)器 3.3V ABT 16B Univ 總線收發(fā)器 RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16500MEA | 功能描述:總線收發(fā)器 UB Transceiver 18Bit RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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