參數(shù)資料
型號(hào): 74LVTH16244LBR
廠(chǎng)商: 意法半導(dǎo)體
英文描述: LOW VOLTAGE BICMOS 16 BIT BUS BUFFER WITH BUS HOLD AND POWER UP 3-STATE
中文描述: 低電壓BICMOS工藝的16位總線(xiàn)緩沖器與巴士持有和功率增加了3態(tài)
文件頁(yè)數(shù): 6/13頁(yè)
文件大小: 199K
代理商: 74LVTH16244LBR
74LVTH16244
6/13
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device
switching in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|
2) Parameter guaranteed by design
CAPACITANCE CHARACTERISTICS
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
= 2.7V
V
CC
= 3.3
±
0.3V
Min.
Max.
Min.
Typ.
Max.
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
t
OSLH
t
OSHL
Propagation Delay Time An to Yn
Propagation Delay Time An to Yn
Output Enable Time nG to Yn
Output Enable Time nG to Yn
Output Disable Time nG to Yn
Output Disable Time nG to Yn
Output To Output Skew Time
(note1, 2)
T
A
= - 40 to 85 °C
3.7
3.7
5.0
5.0
4.4
5.0
1.2
1.2
1.2
1.2
2.0
2.2
2.5
2.5
2.7
2.7
3.7
4.4
3.2
3.2
4.0
4.0
4.2
5.1
0.5
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 °C
-40 to 85 °C
Min.
Typ.
Max.
Min.
Max.
C
I
C
O
Control Input Capacitance
Output Capacitance
open
3.3
6
pF
pF
15
TEST
SWITCH
t
PLH
, t
PHL
t
PZL
, t
PLZ
(V
CC
= 3.0 to 3.6V)
t
PZL
, t
PLZ
(V
CC
= 2.7V)
t
PZH
, t
PHZ
Open
6V
6V
GND
相關(guān)PDF資料
PDF描述
74LVTH16244TTR LOW VOLTAGE BICMOS 16 BIT BUS BUFFER WITH BUS HOLD AND POWER UP 3-STATE
74LVTH16244 Octal Bus Transceivers With 3-State Outputs 20-SO -40 to 85
74LVTH16244 Octal Bus Transceivers With 3-State Outputs 20-PDIP -40 to 85
74LVTH16244MEA Octal Bus Transceivers With 3-State Outputs 20-SO -40 to 85
74LVTH16244MTD Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
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