- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369321 > 74LVQ280M (意法半導(dǎo)體) 9 BIT PARITY GENERATOR PDF資料下載
參數(shù)資料
| 型號(hào)： | 74LVQ280M |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 9 BIT PARITY GENERATOR |
| 中文描述： | 9位奇偶發(fā)生器 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 229K |
| 代理商： | 74LVQ280M |
1/8
July 2001
I
HIGH SPEED:
t
PD
= 8 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 2
μ
A(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
75
TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
The 74LVQ280 is a low voltage CMOS 9 BIT
PARITY GENERATOR fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (
Σ
ODD and
Σ
EVEN). The nine
data inputs control the output conditions. When
the number of high level input is odd,
Σ
ODD
output is kept high and
Σ
EVEN output low.
Conversely, when the number of high level is
even,
Σ
EVEN output is kept high and
Σ
ODD low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easily expanded by cascading.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ280
9 BIT PARITY GENERATOR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
TSSOP
74LVQ280M
74LVQ280MTR
74LVQ280TTR
TSSOP
SOP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVQ280MTR | 9 BIT PARITY GENERATOR |
| 74LVQ280TTR | 9 BIT PARITY GENERATOR |
| 74LVQ299MTR | 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR |
| 74LVQ299TTR | 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR |
| 74LVQ32M | QUAD 2-INPUT OR GATE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVQ280MTR | 功能描述:奇偶功能 9-Bit Parity Gen RoHS:否 制造商:Texas Instruments 電路數(shù)量:1 位數(shù):9 邏輯系列:74AC 封裝 / 箱體:SOIC-14 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:263 ns 工作電源電壓:1.8 V, 2.5 V, 3.3 V, 5 V 最大工作溫度:+ 70 C 最小工作溫度:- 55 C 封裝:Reel |
| 74LVQ299TTR | 功能描述:計(jì)數(shù)器移位寄存器 8-Bit PIPO Shift Reg RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74LVQ32M | 功能描述:邏輯門 Quad 2-Input OR Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74LVQ32MTR | 功能描述:邏輯門 Quad 2-Input OR Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74LVQ32SC | 功能描述:邏輯門 Quad 2-Input OR Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。