參數(shù)資料
型號: 74LVQ299TTR
廠商: 意法半導(dǎo)體
英文描述: 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
中文描述: 8位皮普移位寄存器帶異步清零
文件頁數(shù): 1/15頁
文件大小: 346K
代理商: 74LVQ299TTR
1/15
July 2004
I
HIGH SPEED:
t
PD
= 8.3 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 4
μ
A (MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.5V (TYP.) at V
CC
= 3.3V
75
TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 299
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
The 74LVQ299 is a low voltage CMOS 8 BIT
PIPO SHIFT REGISTER (3-STATE) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power and low noise 3.3V applications.
These devices have four modes (HOLD, SHIFT
LEFT, SHIFT RIGHT and LOAD DATA). Each
mode is chosen by two function select inputs (S0,
S1) as shown in the Truth Table.
When one or both enable inputs, (G1, G2) are
high, the eight input/output terminals are in the
high impedance state; however sequential
operation or clearing of the register is not affected.
Clear function is asynchronous to clock.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ299
8 BIT PIPO SHIFT REGISTER
WITH ASYNCHRONOUS CLEAR
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
TSSOP
74LVQ299MTR
74LVQ299TTR
TSSOP
SOP
Rev. 2
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