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參數(shù)資料
| 型號(hào)： | 74LVC1G58GV,125 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CONFIG MULTIPLE FUNCT 6TSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | 74LVC |
| 邏輯類型： | 可配置多功能 |
| 電路數(shù)： | 1 |
| 輸入數(shù)： | 3 |
| 施密特觸發(fā)器輸入： | 是 |
| 輸出類型： | 單端 |
| 輸出電流高，低： | 32mA，32mA |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74，SOT-457 |
| 供應(yīng)商設(shè)備封裝： | 6-TSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74LVC1G58GV-G 74LVC1G58GV-G-ND 935276074125 |
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AR1000 SERIES RESISTIVE TOUCH SCREEN CONTROLLER
DS41393B-page 18
Preliminary
2009-2012 Microchip Technology Inc.
4.2
I2C Pin Voltage Level
Characteristics
4.3
Addressing
The AR1021’s device ID 7-bit address is: 0x4D
(0b1001101)
4.4
Master Read Bit Timing
Master read is to receive touch reports and command
responses from the AR1021.
Address bits are latched into the AR1021 on the
rising edges of SCL.
Data bits are latched out of the AR1021 on the
rising edges of SCL.
ACK is presented (by AR1021 for address, by
master for data) on the ninth clock.
The master must monitor the SCL pin prior to
asserting another clock pulse, as the AR1021
may be holding off the master by stretching the
clock.
FIGURE 4-1:
I2C MASTER READ BIT TIMING DIAGRAM
Steps
1.
SCL and SDA lines are Idle high.
2.
Master presents “Start” bit to the AR1021 by
taking SDA high-to-low, followed by taking SCL
high-to-low.
3.
Master presents 7-bit Address, followed by a
R/W = 1 (Read mode) bit to the AR1021 on
SDA, at the rising edge of eight master clock
(SCL) cycles.
4.
AR1021 compares the received address to its
device ID. If they match, the AR1021
acknowledges (ACK) the master sent address
by presenting a low on SDA, followed by a
low-high-low on SCL.
5.
Master monitors SCL, as the AR1021 may be
“clock stretching”, holding SCL low to indicate
that the master should wait.
TABLE 4-2:
I2C PIN VOLTAGE LEVEL CHARACTERISTICS
Function
Pin
Input
Output
SCL/SCK
SCL/SCK/TX
VSS ≤ VIL≤ 0.2*VDD
0.8*VDD ≤ VIH ≤ VDD
—
SDO
—
VSS ≤ VOL(1) ≤ (1.2V – 0.15*VDD)(2)
(1.25*VDD – 2.25V)(3) ≤ VOH(1) ≤ VDD
SDA
SDI/SDA/RX
VSS ≤ VIL ≤ 0.2*VDD
0.8*VDD ≤ VIH ≤ VDD
Open-drain
Note 1:
These parameters are characterized but not tested.
2:
At 10 mA.
3:
At –4 mA.
TABLE 4-3:
I2C DEVICE ID ADDRESS
Device ID Address, 7-bit
A7
A6
A5
A4
A3
A2
A1
10
0
1
0
1
TABLE 4-4:
I2C DEVICE WRITE ID
ADDRESS
A7
A6
A5
A4 A3 A2 A1 A0
1
0
1
010
0x9A
TABLE 4-5:
I2C DEVICE READ ID
ADDRESS
A7
A6
A5
A4 A3 A2 A1 A0
1
0
1
011
0x9B
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