參數(shù)資料
型號: 74LVC169DB,112
廠商: NXP Semiconductors
文件頁數(shù): 20/24頁
文件大?。?/td> 0K
描述: IC SYNC 4BIT BIN COUNTER 16SSOP
產(chǎn)品培訓模塊: Logic Packages
標準包裝: 78
系列: 74LVC
邏輯類型: 二進制計數(shù)器
方向: 上,下
元件數(shù): 1
每個元件的位元數(shù): 4
計時: 同步
計數(shù)速率: 150MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
其它名稱: 74LVC169DB
74LVC169DB-ND
935210580112
74LVC169
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 29 November 2012
5 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
5.
Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO16 and (T)SSOP16
Fig 5.
Pin configuration for DHVQFN16
74LVC169
U/D
VCC
CP
TC
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CEP
CET
GND
PE
001aaa644
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aaa682
74LVC169
CEP
CET
D3
Q3
D2
GND(1)
Q2
D1
Q1
D0
Q0
CP
TC
GND
PE
U/D
V
CC
Transparent top view
7
10
6
11
5
12
4
13
3
14
2
15
8
9
1
16
terminal 1
index area
Table 2.
Pin description
Symbol
Pin
Description
U/D
1
up/down control input
CP
2
clock input (LOW-to-HIGH, edge-triggered)
D0 to D3
3, 4, 5, 6
data input
CEP
7
count enable input (active LOW)
GND
8
ground (0 V)
PE
9
parallel enable input (active LOW)
CET
10
count enable carry input (active LOW)
Q0 to Q3
14, 13, 12, 11
flip-flop output
TC
15
terminal count output (active LOW)
VCC
16
supply voltage
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