參數(shù)資料
型號(hào): 74LVC169DB,112
廠商: NXP Semiconductors
文件頁數(shù): 12/24頁
文件大小: 0K
描述: IC SYNC 4BIT BIN COUNTER 16SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 78
系列: 74LVC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向: 上,下
元件數(shù): 1
每個(gè)元件的位元數(shù): 4
計(jì)時(shí): 同步
計(jì)數(shù)速率: 150MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
其它名稱: 74LVC169DB
74LVC169DB-ND
935210580112
74LVC169
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 29 November 2012
2 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be
HIGH. The pin U/D input determines the direction of the counting. The terminal count
output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW,
when a counter reaches 15 in the count up mode. The pin TC output state is not a function
of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by
decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For
this reason the use of pin TC as a clock signal is not recommended; see the following
logic equations:
2.
Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Up/down counting
Two count enable inputs for n-bit cascading
Built-in look-ahead carry capability
Presettable for programmable operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from
40 Cto+85 C and from 40 Cto+125 C
count enable
CEP
CET
PE
=
count up: TC
Q3
Q2
Q1
Q0
CET
U D
=
count down: TC
Q3
Q2
Q1
Q0
CET
U D
=
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