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參數(shù)資料
| 型號： | 74LVC163PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable synchronous 4-bit binary counter; synchronous reset |
| 中文描述： | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 74LVC163PWDH |
Philips Semiconductors
Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20
8
AC WAVEFORMS
V
M
= 1.5 V at V
CC
V
M
= 0.5 V
CC
at V
CC
< 2.7 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
2.7 V
V
M
V
M
1/f
MAX
t
w
t
PLH
t
PHL
CP INPUT
GND
Qn, TC OUTPUT
V
OL
SY00071
V
I
V
OH
Waveform 1. Clock (CP) to outputs (Q
n
, TC) propagation
delays, the clock pulse width and the maximum clock
frequency.
V
M
t
PLH
t
PHL
CET INPUT
TC OUTPUT
V
M
V
I
GND
V
OH
V
OL
SY00072
Waveform 2. Input (CET) to output (TC) propagation delays.
V
M
V
M
t
su
t
su
t
h
t
h
MR
INPUT
GND
CP INPUT
GND
SC0013
V
I
V
I
Waveform 3. Master reset (MR) pulse width, the master reset
to output (Q
n
, TC) propagation delays and the master reset to
clock (CP) removal times.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
t
h
t
h
V
M
V
M
V
M
V
I
V
I
V
I
GND
GND
GND
PE INPUT
CP INPUT
D
n
INPUT
t
SU
t
SU
t
h
t
SU
t
h
t
SU
SC00137
Waveform 4. Setup and hold times for the input (D
n
) and
parallel enable input (PE).
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
V
M
V
M
V
M
t
su
t
h
t
su
t
h
SC00138
V
I
V
I
GND
GND
CEP, CET
INPUT
CP INPUT
Waveform 5. CEP and CET setup and hold times.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
V
CC
500
Open
GND
S
1
V
CC
V
I
< 2.7V
V
CC
TEST
S
1
t
PLH/
t
PHL
Open
2.7V
2.7–3.6V
50pF
500
2 * V
CC
SV00903
Waveform 6. Load circuitry for switching times.
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