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參數(shù)資料
| 型號： | 74LVC163PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable synchronous 4-bit binary counter; synchronous reset |
| 中文描述： | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 74LVC163PWDH |
Philips Semiconductors
Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20
4
FUNCTIONAL DIAGRAM
PARALLEL LOAD
CIRCUITRY
BINARY
COUNTER
3
4
5
6
TC 15
14
13
12
11
Q
0
Q
1
Q
2
Q
3
1
MR
2
CP
7
D
0
D
1
D
2
D
3
CEP
CET
10
PE
9
SY00068
STATE DIAGRAM
8
7
6
5
4
12
11
10
9
13
14
15
0
1
2
3
SF00664
FUNCTION TABLE
OPERATING
MODES
INPUTS
OUTPUTS
MR
CP
CEP
CET
PE
Dn
Qn
TC
Reset (clear)
l
↑
X
X
X
X
L
L
Parallel load
h
h
↑
↑
X
X
X
X
l
l
l
L
H
L
*
h
Count
h
↑
h
h
h
X
count
*
Hold
h
h
X
X
l
X
l
h
h
X
X
q
n
q
n
*
L
(do nothing)
NOTES:
*
=
X
The TC output is High when CET is High and the counter
is at Terminal Count (HHHH)
High voltage level
High voltage level one setup time prior to the Low-to-High
clock transition
Low voltage level
Low voltage level one setup time prior to the Low-to-High
clock transition
Lower case letters indicate the state of the referenced
output one setup time prior to the Low-to-High clock
transition
Don’t care
Low-to-High clock transition
H
h
=
=
L
l
=
=
q
=
X
↑
=
=
TYPICAL TIMING SEQUENCE
CP
PE
TC
MR
INHIBIT
COUNT
CEP
CET
D0
D2
D1
D3
Q0
Q2
Q1
Q3
RESET PRESET
12
13
14
15
0
1
2
SY00069
Typical timing sequence: reset outputs to zero; preset to binary
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit
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