參數(shù)資料
型號(hào): 74LVC16244ADGG,112
廠商: NXP Semiconductors
文件頁數(shù): 1/19頁
文件大小: 0K
描述: IC BUFF DVR TRI-ST 16BIT 48TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 39
系列: 74LVC
邏輯類型: 緩沖器/線路驅(qū)動(dòng)器,非反相
元件數(shù): 4
每個(gè)元件的位元數(shù): 4
輸出電流高,低: 24mA,24mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 管件
其它名稱: 568-8316-5
74LVC16244ADG
74LVC16244ADG-ND
74LVC16244ADGG,112-ND
74LVC16244ADGG,512
74LVC16244ADGG,512-ND
935235150112
1.
General description
The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with
3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit
buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each
controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a
high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2.
Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
High-impedance when VCC =0V
All data inputs have bus hold. (74LVCH16244A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 Cto+85 C and 40 Cto+125 C
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Rev. 13 — 7 February 2014
Product data sheet
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