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參數(shù)資料
| 型號： | 74LV74PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual D-type flip-flop with set and reset; positive-edge trigger |
| 中文描述： | LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | PLASTIC, TSSOP1-14 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 125K |
| 代理商： | 74LV74PWDH |
Philips Semiconductors
Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5 * V
CC
at V
CC
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
2.7V
3.6V
2.7V and
4.5V
GND
h
h
nQ OUTPUT
nD INPUT
nCP INPUT
nQ OUTPUT
V
M
V
M
V
M
t
su
1/f
max
t
PHL
t
PHL
t
PLH
t
PLH
t
W
GND
V
I
V
I
V
OL
V
OL
V
OH
V
OH
t
su
SV00335
Figure 1.The clock (nCP) to output (nQ, nQ) propagation
delays, the clock pulse width, the nD to nCP setup times, the
nCP to nD hold times, the output transition times and the
maximum clock pulse frequency
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
nCP INPUT
nS
D
INPUT
nR
D
INPUT
nQ OUTPUT
nQ OUTPUT
GND
GND
GND
V
I
V
I
V
I
V
OL
V
OL
V
OH
V
OH
V
M
V
M
V
M
V
M
t
rem
t
PHL
t
PLH
t
W
t
W
V
M
t
PLH
t
PHL
SV00336
Figure 2.The set (nS
D
) and reset (nR
D
) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths and the nR
D
to nCP removal time
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
l
D.U.T.
V
O
C
L
R
L
= 1k
V
cc
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
V
I
< 2.7V
2.7–3.6V
V
CC
2.7V
TEST
t
PLH/
t
PHL
≥
4.5 V
V
CC
50pF
SV00902
Figure 3. Load circuitry for switching times
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