V
參數(shù)資料
型號: 74LV393PW,112
廠商: NXP Semiconductors
文件頁數(shù): 10/12頁
文件大?。?/td> 0K
描述: IC DUAL 4BIT BINAR RIPPL 14TSSOP
產(chǎn)品培訓模塊: Logic Packages
標準包裝: 96
系列: 74LV
邏輯類型: 二進制計數(shù)器
方向:
元件數(shù): 2
每個元件的位元數(shù): 4
復位: 異步
計數(shù)速率: 20MHz
觸發(fā)器類型: 負邊沿
電源電壓: 1 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 14-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 838 (CN2011-ZH PDF)
其它名稱: 568-2968-5
935198250112
Philips Semiconductors
Product specification
74LV393
Dual 4-bit binary ripple counter
1998 Jun 10
7
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V
VM = 0.5 * VCC at VCC t 2.7V
VOL and VOH are the typical output voltage drop that occur with the
output load.
SV00678
VM
nCP INPUT
VCC
GND
VOH
VOL
nQn OUTPUT
VM
tPLH
tPHL
1/fmax
Figure 1. Clock (nCP) to output (1Qn, 2Qn) propagation delays,
the clock pulse width, and the maximum clock frequency
SV00679
VM
nMR INPUT
nCP INPUT
VCC
GND
VOL
VOH
nQn OUTPUT
VM
trem
tPHL
tW
Figure 2. Master reset (nMR) pulse width,
the master reset to output (Qn) propagation delays,
and the master reset to clock (nCP) removal time
TEST CIRCUIT
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
RL = 1k
VCC
Test Circuit for switching times
DEFINITIONS
VCC
VI
< 2.7V
VCC
TEST
tPLH/tPHL
RT = Termination resistance should be equal to ZOUT of pulse generators.
50pF
SV00901
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
2.7–3.6V
2.7V
Figure 3. Load circuitry for switching times
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