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參數(shù)資料
| 型號(hào)： | 74LV164 |
| 廠(chǎng)商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit serial-in/parallel-out shift register(8位串入并出移位寄存器) |
| 中文描述： | 8位serial-in/parallel-out移位寄存器（8位串入并出移位寄存器） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 119K |
| 代理商： | 74LV164 |
Philips Semiconductors
Product specification
74LV164
8-bit serial-in/parallel-out shift register
2
1998 May 07
853–1961 19349
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot)
T
amb
= 25
°
C
Gated serial data inputs
Asynchronous master reset
Output capability: standard
I
CC
category: MSI
0.8V @ V
CC
= 3.3V,
2V @ V
CC
= 3.3V,
DESCRIPTION
The 74LV164 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (D
sa
or D
sb
); either input can be
used as an active HIGH enable for data entry through the other
input. Both inputs must be connected together or an unused input
must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of
the clock (CP) input and enters into Q
0
, which is the logical AND of
the two data inputs (D
sa
, D
sb
) that existed one set-up time prior to
the rising clock edge.
A LOW on the master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all outputs LOW.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n
MR to Q
n
C
L
= 15pF
V
CC
= 3.3V
12
12
ns
f
max
C
I
Maximum clock frequency
78
MHz
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per gate
V
= 3.3V
Notes 1 and 2
40
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°
C to +125
°
C
74LV164 N
74LV164 N
SOT27-1
14-Pin Plastic SO
–40
°
C to +125
°
C
74LV164 D
74LV164 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV164 DB
74LV164 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LV164 PW
74LV164PW DH
SOT402-1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV164A | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS |
| 74LV164BQ | 制造商:NXP Semiconductors 功能描述:Shift Register Single 8-Bit Serial to Parallel 14-Pin DHVQFN EP T/R Bulk 制造商:NXP Semiconductors 功能描述:IC 8BIT SIPO SHIFT REG DHV |
| 74LV164BQ,115 | 功能描述:計(jì)數(shù)器移位寄存器 3.3V 8-BIT SI-PO RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類(lèi)型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類(lèi)型: 輸入線(xiàn)路數(shù)量:1 輸出類(lèi)型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74LV164BQ-G | 功能描述:計(jì)數(shù)器移位寄存器 3.3V 8-BIT SI-PO SHIFT REG RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類(lèi)型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類(lèi)型: 輸入線(xiàn)路數(shù)量:1 輸出類(lèi)型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74LV164BQ-Q100X | 制造商:NXP Semiconductors 功能描述:74LV164BQ-Q100/DHVQFN14/REEL7/ - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC SHIFT REGISTER 8BIT 14DHVQFN |
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