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參數(shù)資料
| 型號： | 74LS138 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Decoder/Demultiplexer |
| 中文描述： | 解碼器/解復用器 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 81K |
| 代理商： | 74LS138 |
2000 Fairchild Semiconductor Corporation
DS006391
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS138 DM74LS139
Decoder/Demultiplexer
General Description
These Schottky-clamped circuits are designed to be used
in high-performance memory-decoding or data-routing
applications, requiring very short propagation delay times.
In high-performance memory systems these decoders can
be used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of
the memory. This means that the effective system delay
introduced by the decoder is negligible.
The DM74LS138 decodes one-of-eight lines, based upon
the conditions at the three binary select inputs and the
three enable inputs. Two active-low and one active-high
enable inputs reduce the need for external gates or invert-
ers when expanding. A 24-line decoder can be imple-
mented with no external inverters, and a 32-line decoder
requires only one inverter. An enable input can be used as
a data input for demultiplexing applications.
The DM74LS139 comprises two separate two-line-to-four-
line decoders in a single package. The active-low enable
input can be used as a data line in demultiplexing applica-
tions.
All of these decoders/demultiplexers feature fully buffered
inputs, presenting only one normalized load to its driving
circuit. All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify sys-
tem design.
Features
I
Designed specifically for high speed:
Memory decoders
Data transmission systems
I
DM74LS138 3-to-8-line decoders incorporates 3 enable
inputs to simplify cascading and/or data reception
I
DM74LS139 contains two fully independent 2-to-4-line
decoders/demultiplexers
I
Schottky clamped for high performance
I
Typical propagation delay (3 levels of logic)
DM74LS138
21 ns
DM74LS139
21 ns
I
Typical power dissipation
DM74LS138
32 mW
DM74LS139
34 mW
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
DM74LS138M
DM74LS138SJ
DM74LS138N
DM74LS139M
DM74LS139SJ
DM74LS139N
Package Number
M16A
M16D
N16E
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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| 74LS138 WAF | 制造商:Texas Instruments 功能描述: |
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