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參數(shù)資料
| 型號(hào)： | 74HCT40105 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-Bit Parallel-Load Shift Registers 16-SOIC -40 to 85 |
| 中文描述： | 4位× 16字FIFO寄存器 |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 200K |
| 代理商： | 74HCT40105 |
1998 Jan 23
11
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
Fig.6
Waveforms showing the SI input to DIR output propagation
delay. The SI pulse width and SI maximum pulse frequency.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Notes to
Fig.6
1.
DIR initially HIGH; FIFO is
prepared for valid data.
SI set HIGH; data loaded into
input stage.
DIR drops LOW, input stage
“busy”.
DIR goes HIGH, status flag
indicates FIFO prepared for
additional data; data from first
location “ripple through”.
SI set LOW; necessary to
complete shift-in process.
Repeat process to load 2nd word
through to 16th word into FIFO.
DIR remains LOW: with attempt
to shift into full FIFO, no data
transfer occurs.
2.
3.
4.
5.
6.
7.
With FIFO full; SI held HIGH in anticipation of empty location
Fig.7
Waveforms showing bubble-up delay, SO input to DIR output
and DIR output pulse width.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Notes to
Fig.7
1.
FIFO is initially, shift-in is held
HIGH.
SO pulse; data in the output
stage is unloaded, “bubble-up
process of empty locations
begins”.
DIR HIGH; when empty location
reached input stage, flag
indicates FIFO is prepared for
data input.
DIR returns to LOW; FIFO is full
again.
SI brought LOW; necessary to
complete whidt-in process, DIR
remains LOW, because FIFO is
full.
2.
3.
4.
5.
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| 74HCT40105D | 功能描述:寄存器 4-BIT X 16 WORD FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT40105D,112 | 功能描述:寄存器 4-BIT X 16 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT40105D,118 | 功能描述:寄存器 4-BIT X 16 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT40105DB | 功能描述:寄存器 4-BIT X 16 WORD FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT40105DB,112 | 功能描述:寄存器 4-BIT X 16 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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