參數(shù)資料
型號(hào): 74HC74DR2G
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
中文描述: HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝: LEAD FREE, SOIC-14
文件頁數(shù): 1/8頁
文件大?。?/td> 143K
代理商: 74HC74DR2G
Semiconductor Components Industries, LLC, 2007
February, 2007
Rev. 0
1
Publication Order Number:
74HC74/D
74HC74
Dual D FlipFlop with Set
and Reset
High
Performance Silicon
Gate CMOS
The 74HC74 is identical in pinout to the LS74. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
This device consists of two D flip
flops with individual Set, Reset,
and Clock inputs. Information at a D
input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip
flop. The Set
and Reset inputs are asynchronous.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7A Requirements
ESD Performance: HBM 2000 V; Machine Model 200 V
Chip Complexity: 128 FETs or 32 Equivalent Gates
Pb
Free Packages are Available
http://onsemi.com
MARKING
DIAGRAMS
HC74
A
L, WL
Y
W, WW
G or
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb
Free Package
TSSOP
14
DT SUFFIX
CASE 948G
14
1
SOIC
14
D SUFFIX
CASE 751A
14
1
HC74G
AWLYWW
1
14
HC
74
ALYW
1
14
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
相關(guān)PDF資料
PDF描述
74HC74DTR2 Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
74HC74DTR2G Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
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74HC86A Quad 2−Input Exclusive OR Gate High−Performance Silicon−Gate CMOS
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