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參數(shù)資料
| 型號： | 74HC652PW,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSCVR 3ST 8BIT INV 24TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 63 |
| 系列： | 74HC |
| 邏輯類型： | 收發(fā)器，反相 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 輸出電流高，低： | 7.8mA，7.8mA |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 74HC652PW 74HC652PW-ND 935248860112 |
September 1993
2
Philips Semiconductors
Product specication
Octal bus transceiver/register; 3-state
74HC/HCT652
FEATURES
Multiplexed real-time and stored
data
Independent register for A and B
buses
Independent enables for A and B
buses
3-state
Output capability: Bus driver
Low power consumption by CMOS
technology
ICC category: MSI.
APPLICATIONS
Bus interfaces.
DESCRIPTION
The 74HC/HCT652 are high-speed
SI-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with Jedec standard
no. 7A.
The 74HC/HCT652 consist of 8
non-inverting bus transceiver circuits
with 3-state outputs, D-type flip-flops
and central circuitry arranged for
multiplexed transmission of data
directly from the data bus or from the
internal storage registers. Data on the
“A” or “B” or both buses, will be stored
in the internal registers, at the
appropriate clock pins (CPAB or
CPBA) regardless of the select pins
(SAB and SBA) or output enable (OEAB
and OEBA) control pins. Depending
on the select inputs SAB and SBA data
can directly go from input to output
(real time mode) or data can be
controlled by the clock (storage
mode), this is when the output enable
pins this operating mode permits. The
output enable pins OEAB and OEBA
determine the operation mode of the
transceiver. When OEAB is LOW, no
data transmission from An to Bn is
possible and when OEBA is HIGH,
there is no data transmission from Bn
to An possible. When SAB and SBA are
in the real time transfer mode, it is
also possible to store data without
using the internal D-type flip-flops by
simultaneously enabling OEAB and
OEBA. In this configuration each
output reinforces its input. Thus when
all other data sources to the two sets
of bus lines are at high-impedance,
each set of the bus lines will remain at
its last state. This type differs from the
HC/HCT646 in one extra
bus-management function. This is the
possibility to transfer stored “A data to
the “B” bus and transfer stored ”B”
data to the ”A” bus at the same time.
The examples at the application
information demonstrate all bus
management functions.
Schmitt-trigger action in the clock
inputs makes the circuit highly
tolerant to slower clock rise and fall
times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr =tf = 6 ns; VCC = 4.5 V; CL = 50 pF.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
∑ (CL × VCC2 × fo) = sum of the outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPLH/tPZL
propagation delay An/Bn to Bn /An
CL = 15 pF;
VCC =5 V
13
ns
propagation delay CPAB/CPBA to Bn /An
18
20
ns
propagation delay SAB/SBA to Bn /An
20
23
ns
tPHZ/tPZL
3-state output enable time OEAB/OEBA to Bn/An
14
15
ns
tPHZ/tPLZ
3-state output disable time OEAB/OEBA to Bn/An
12
13
ns
fmax
maximum clock frequency
92
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per channel
notes 1 and 2
26
28
pF
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