參數(shù)資料
型號(hào): 74HC595
廠商: NXP Semiconductors N.V.
英文描述: 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state
中文描述: 8位serial-in/serial或并行輸出的移位寄存器輸出鎖存器,三態(tài)
文件頁數(shù): 2/20頁
文件大小: 122K
代理商: 74HC595
1998 Jun 04
2
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
FEATURES
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typ) shift out frequency
Output capability:
– parallel outputs; bus driver
– serial output; standard
I
CC
category: MSI.
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register.
DESCRIPTION
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “595” is an 8-stage serial shift register with a storage
register and 3-state outputs. The shift register and storage
register have separate clocks.
Data is shifted on the positive-going transitions of the
SH
CP
input. The data in each register is transferred to the
storage register on a positive-going transition of the ST
CP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (D
S
) and a serial
standard output (Q
7
’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
1.5 V.
2.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
HC
HCT
t
PHL
/t
PLH
propagation delay
SH
CP
to Q
7
ST
CP
to Q
n
MR to Q
7
maximum clock frequency SH
CP
, ST
CP
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
16
17
14
100
3.5
115
21
20
19
57
3.5
130
ns
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
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