參數(shù)資料
型號: 74HC595
廠商: NXP Semiconductors N.V.
英文描述: 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state
中文描述: 8位serial-in/serial或并行輸出的移位寄存器輸出鎖存器,三態(tài)
文件頁數(shù): 11/20頁
文件大小: 122K
代理商: 74HC595
1998 Jun 04
11
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
SYMBOL PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITION
+
25
40 to
+
85
40 to
+
125
V
CC
(V)
WAVEFORMS
min
typ
max
min
max
min
max
t
PHL
/ t
PLH
propagation delay
SH
CP
to Q
7
propagation delay
ST
CP
to Q
n
propagation delay
MR to Q
7
3-state output enable
time OE to Q
n
3-state output disable
time OE to Q
n
shift clock pulse
width HIGH or LOW
storage clock pulse width
HIGH or LOW
master reset
pulse width LOW
set-up time D
S
to
SH
SP
set-up time SH
CP
to ST
CP
hold time D
S
to SH
CP
25
42
53
63
ns
4.5
Fig.7
t
PHL
/ t
PLH
24
40
50
60
ns
4.5
Fig.8
t
PHL
23
40
50
60
ns
4.5
Fig.10
t
PZH
/ t
PZL
21
35
44
53
ns
4.5
Fig.11
t
PHZ
/ t
PLZ
18
30
38
45
ns
4.5
Fig.11
t
W
16
6
20
24
ns
4.5
Fig.7
t
W
16
5
20
24
ns
4.5
Fig.8
t
W
20
8
25
30
ns
4.5
Fig.10
t
su
16
5
20
24
ns
4.5
Fig.9
t
su
16
8
20
24
ns
4.5
Fig.8
t
h
3
2
3
3
ns
4.5
Fig.9
t
rem
removal time MR
to SH
CP
maximum clock
pulse frequency
SH
CP
or ST
CP
10
7
13
15
ns
4.5
Fig.10
f
max
30
52
24
20
MHz
4.5
Figs 7 and 8
相關(guān)PDF資料
PDF描述
74HCT595 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-TSSOP -40 to 85
74HC595 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATE
74HC595 8-bit Shift Register/Latch (with 3-state outputs)
74HC595 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
74HC595 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High–Performance Silicon–Gate CMOS
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