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參數(shù)資料
| 型號： | 74HC4024DB,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 7STAGE BINARY RIPPLE 14SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 74HC |
| 邏輯類型： | 二進制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 7 |
| 復(fù)位： | 異步 |
| 計數(shù)速率： | 90MHz |
| 觸發(fā)器類型： | 負(fù)邊沿 |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74HC4024DB-T 74HC4024DB-T-ND 935189980118 |
74HC4024
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 31 October 2013
10 of 19
NXP Semiconductors
74HC4024
7-stage binary ripple counter
[1]
tpd is the same as tPLH and tPHL.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD VCC2 fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(C
L VCC
2
f
o) = sum of outputs.
12. Waveforms
fmax
maximum frequency
CP; see Figure 6
VCC = 2.0 V
4.0
--MHz
VCC = 4.5 V
20
--MHz
VCC = 6.0 V
24
--MHz
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr =tf =6 ns; CL = 50 pF; see Figure 7.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to
clock (CP) recovery time.
VM = 0.5 VI.
Fig 6.
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
MR input
CP input
Q0 or Qn
output
tW
tPHL
1/fmax
trec
VM
001aab910
tPLH
tW
tTLH
tTHL
tPHL
VM
90 %
10 %
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