參數(shù)資料
型號(hào): 74HC4024DB,118
廠商: NXP Semiconductors
文件頁數(shù): 13/19頁
文件大?。?/td> 0K
描述: IC 7STAGE BINARY RIPPLE 14SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,000
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 7
復(fù)位: 異步
計(jì)數(shù)速率: 90MHz
觸發(fā)器類型: 負(fù)邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 14-SSOP
包裝: 帶卷 (TR)
其它名稱: 74HC4024DB-T
74HC4024DB-T-ND
935189980118
74HC4024
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 31 October 2013
3 of 19
NXP Semiconductors
74HC4024
7-stage binary ripple counter
6.
Pinning information
6.1 Pinning
6.2 Pin description
7.
Functional description
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition.
Fig 5.
Pin configuration
74HC4024
CP
VCC
MR
n.c.
Q6
Q0
Q5
Q1
Q4
n.c.
Q3
Q2
GND
n.c.
001aab905
1
2
3
4
5
6
7
8
10
9
12
11
14
13
Table 2.
Pin description
Symbol
Pin
Description
CP
1
clock input (HIGH-to-LOW, edge-triggered)
MR
2
master reset input (active HIGH)
Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0
3, 4, 5, 6, 9, 11, 12
parallel output
GND
7
ground (0 V)
n.c.
8, 10, 13
not connected
VCC
14
positive supply voltage
Table 3.
Function table[1]
Input
Output
MR
CP
Qn
HX
L
no change
count
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