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參數(shù)資料
| 型號： | 74HC297D-T |
| 英文描述： | Analog Phase-Locked Loop |
| 中文描述： | 模擬鎖相環(huán) |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 83K |
| 代理商： | 74HC297D-T |
2003 May 14
2
Philips Semiconductors
Product specification
Dual 2-input NOR gate
74HC2G02; 74HCT2G02
FEATURES
Wide supply voltage range from 2.0 to 6.0 V
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Very small 8 pins package
Output capability is standard
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
40 to +85
°
C and
40 to +125
°
C.
DESCRIPTION
The 74HC2G/HCT2G02 is a high-speed Si-gate CMOS
device.
The 74HC2G/HCT2G02 provides the 2-input NOR
function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
6.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
For 74HC2G02 the condition is V
I
= GND to V
CC
.
For 74HCT2G02 the condition is V
I
= GND to V
CC
1.5 V.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC2G02
HCT2G02
t
PHL
/t
PLH
C
I
C
PD
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate notes 1 and 2
C
L
= 15 pF; V
CC
= 5 V
9
1.5
10
12
1.5
10
ns
pF
pF
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