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參數(shù)資料
| 型號： | 74F777 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple bidirectional latched bus transceiver (3-State + open collector)(三通道雙向鎖存總線收發(fā)器（三態(tài)+集電極開路）) |
| 中文描述： | 三鎖存總線雙向收發(fā)器（3態(tài)集電極開路）（三通道雙向鎖存總線收發(fā)器（三態(tài)集電極開路）） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | 74F777 |
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver (3–State +
Open Collector)
2
May 19, 1992
853–1645 06772
FEATURES
Latching transceiver
High drive Open Collector output current with minimum output
swing
Compatible with Test Mode (TM) bus specification
Controlled output ramp
Multiple package options
Industrial temperature range available (–40
°
C to +85
°
C)
DESCRIPTION
The 74F777 is a triple bidirectional latched bus transceiver and is
intended to provide the electrical interface to a high performance
wired–OR bus. This bus has a loaded characteristics impedance
range of 20 to 50 ohms and is terminated on each end with a 30 to
40 ohm resistor.
The 74F777 is a triple bidirectional transceiver with Open Collector
B and 3–State A port output drivers. A latch function is provided for
the A port signals. The B port output driver is designed to sink
100mA from 2 volts to minimize crosstalk and ringing on the bus.
A separate output threshold clamp voltage (V
X
) is provided to
prevent the A port output High level from exceeding future high
density processor supply voltage levels. For 5 volt systems, V
X
is
simply tied to V
CC.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY CUR-
RENT( TOTAL)
74F777
7.0ns
45mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
INDUSTRIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= –40
°
C to +85
°
C
PKG DWG #
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
20–pin plastic DIP (300 mil)
N74F777N
I74F777N
SOT146-1
20–pin PLCC
N74F777A
I74F777A
SOT380-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A2
PNP latched inputs
3.5/0.117
70
μ
A
/
70
μ
A
100
μ
A/100
μ
A
B0 – B2
Data inputs with threshold circuitry
5.0/0.167
OEA0 – OEA2
A output enable inputs (active–High)
1.0/0.033
20
μ
A/20
μ
A
OEB0 – OEB2
B output enable inputs (active–Low)
1.0/0.033
20
μ
A/20
μ
A
LE0 – LE2
Latch enable inputs (active–Low)
1.0/0.033
20
μ
A/20
μ
A
A0 – A2
3–State outputs
150/40
3mA/24mA
B0 – B2
Open Collector outputs
OC/166.7
OC/100mA
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
OC = Open Collector.
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