- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄360442 > 74F657 (NXP Semiconductors N.V.) Octal transceiver with 8-bit parity generator/checker(帶8位奇偶發(fā)生器/校驗(yàn)器的八收發(fā)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | 74F657 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal transceiver with 8-bit parity generator/checker(帶8位奇偶發(fā)生器/校驗(yàn)器的八收發(fā)器) |
| 中文描述： | 八路收發(fā)器帶有8位奇偶發(fā)生器/檢查（帶8位奇偶發(fā)生器/校驗(yàn)器的八收發(fā)器） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 109K |
| 代理商： | 74F657 |
Philips Semiconductors
Product specification
74F657
Octal transceiver with 8-bit parity generator/checker
2
90 July 30
853 1117 00081
FEATURES
Combines 74F245 and 74F280A functions in one package
High impedance base input for reduced loading (70
μ
A in
high and low states)
Ideal in applications where high output drive and light bus
loading are required (I
IL
is 70
μ
A vs FAST std of 600
μ
A)
3–state buffer outputs sink 64mA and source 15mA
Input diodes for termination effects
24–pin plastic slim DIP (300mil) package
Industrial temperature range available (–40
°
C to +85
°
C)
DESCRIPTION
The 74F657 is an octal transceiver featuring non–inverting
buffers with 3–state outputs and an 8–bit parity
generator/checker, and is intended for bus–oriented
applications. The buffers have a guaranteed current sinking
capability of 24mA at the A ports and 64mA at the B ports.
The transmit/receive (T/R) input determines the direction of
the data flow through the bidirectional transceivers.
Transmit (active high) enables data from A ports to B ports;
receive (active low) enables data from B ports to A ports.
The output enable (OE) input disables both the A and B ports by
placing them in a high impedance condition when the OE input is
high
.
The parity select (ODD/EVEN) input gives the user the option of
odd or even parity systems
.
The parity (PARITY) pin is an output from the generator/checker
when transmitting from the port A to B (T/R = high) and an input
when receiving from port B to A port ( T/R = low).
When transmitting (T/R = high) the parity select (ODD/EVEN) input
is set, then the A port data is polled to determined the number of
high bits. The parity (PARITY) output then goes to the logic state
determined by the parity select (ODD/EVEN) setting and by the
number of high bits on port A.
For example, if the parity select (ODD/EVEN) is set low (even
parity), and the number of high bits on port A is odd, then the parity
(PARITY) output will be high, transmitting even parity. If the number
of high bits on port A is even, then the parity (PARITY) output will
be low, keeping even parity.
When in receive mode (T/R = low) the B port is polled to determine
the number of high bits. If parity select (ODD/EVEN) is low (even
parity) and the number of highs on port B is:
(1) odd and the parity (PARITY) input is high, then ERROR will be
high, significantly no error.
(2) even and the parity (PARITY) input is high, then ERROR will be
asserted low, indicating an error.
TYPE
TYPICAL PROPAGA-
TION DELAY
TYPICAL SUPPLY
CURRENT( TOTAL)
74F657
8.0ns
100mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F657N
INDUSTRIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= –40
°
C to +85
°
C
I74F657N
DESCRIPTION
PKG DWG #
24–pin plastic slim
DIP (300mil)
SOT222-1
24–pin plastic SOL
N74F657D
I74F657D
SOT137-1
24–pin plastic SSOP
N74F657DB
I74F657DB
SOT340-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
70
μ
A/70
μ
A
A0 – A7
A ports 3–state inputs
3.5/0.117
B0 – B7
B ports 3–state inputs
3.5/0.117
70
μ
A/70
μ
A
PARITY
Parity input
3.5/0.117
70
μ
A/70
μ
A
T/R
Transmit/receive input
2.0/0.066
40
μ
A/40
μ
A
ODD/EVEN
Parity select input
1.0/0.033
20
μ
A/20
μ
A
OE
Output enable input (active low)
2.0/0.066
40
μ
A/40
μ
A
A0 – A7
A ports 3–state outputs
150/40
3.0mA/24mA
B0 – B7
B ports 3–state outputs
750/106.7
15mA/64mA
PARITY
Parity output
750/106.7
15mA/64mA
ERROR
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20
μ
A in the high state and 0.6mA in the low state.
Error output
750/106.7
15mA/64mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F670 | 4 x 4 register file 3-State |
| 74F674 | 16-bit serial/parallel-in, serial-out shift register 3-State |
| 74F676 | 16-bit serial/parallel-in, serial-out shift register (3-State)(16位串行/并行輸入，串行輸出移位寄存器（三態(tài)）) |
| 74F702SC | Single 8-bit Bus Transceiver |
| 54F701DM | Logic IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F657 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F657N | 制造商:Misc 功能描述: |
| 74F657SC | 功能描述:總線收發(fā)器 Octal Bidir Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74F657SCX | 功能描述:總線收發(fā)器 Octal Bidir Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74F657SDC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single 8-bit Bus Transceiver |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。