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參數(shù)資料
| 型號： | 74F649 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal transceiver/register, non-inverting open-collector |
| 中文描述： | 八路收發(fā)器/寄存器，非反相開路集電極 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 74F649 |
Philips Semiconductors
Product specification
74F647/74F649
Octal transceivers/registers (open-collector)
74F647 Octal Transceiver/Register, Non-inverting (Open Collector)
74F649 Octal Transceiver/Register, Inverting (Open Collector)
2
1992 Feb 28
853-0876 05853
FEATURES
High impedance NPN base inputs for reduced loading
(20
μ
A in High and Low states)
Independent registers for A and B buses
Multiplexed real-time and stored data
Choice of non-inverting and inverting data paths
Open Collector outputs
300 mil wide 24-pin Slim Dip package
DESCRIPTION
The 74F647 and 74F649 Transceivers/Registers consist of bus
transceiver circuits with open-collector outputs, D-type flip-flops, and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or from the internal registers. Data on the
A or B bus will be clocked into the registers as the appropriate clock
pin goes to a High logic level. Output Enable (OE) and DIR pins are
provided to control the transceiver function. In the transceiver mode,
data present at the high impedance port may be stored in either the
A or B register or both.
The select (SAB, SBA) controls can multiplex stored and real-time
(transparent mode) data. The DIR determines which bus will receive
data when the Output Enable, OE is active Low. In the isolation
mode (Output Enable, OE = High), data from Bus A may be stored
in the B register and/or data from Bus B may be stored in the A
register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B, may be driven at a time. The following
examples demonstrate the four fundamental bus-management
functions that can be performed with the 74F647 and 74F649.
TYPE
TYPICAL
f
max
TYPICAL SUPPLY CURRENT
(TOTAL)
74F647
65MHz
125mA
74F649
65MHz
125mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
PKG DWG #
24-pin plastic Slim
DIP (300mil)
N74F647N, N74F649N
SOT222-1
24-pin plastic SOL
N74F647D, N74F649D
SOT137-1
PIN CONFIGURATION – 74F647
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
CPBA
SBA
OE
V
CC
GND
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
CPAB
SAB
DIR
SF01196
PIN CONFIGURATION – 74F649
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
CPBA
SBA
OE
V
CC
GND
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
CPAB
SAB
DIR
SF01196
相關PDF資料 |
PDF描述 |
|---|---|
| 74F647 | Octal transceiver/register, non-inverting open-collector |
| 74F64 | 4-2-3-2-input AND-OR-invert gate |
| 74F646MSAX | Single 8-bit Bus Transceiver |
| 74F646SCX | Single 8-bit Bus Transceiver |
| 74F648SCX | Single 8-Bit Inverting Bus Transceiver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74F64DC | 制造商:Fairchild Semiconductor Corporation 功能描述: 制造商:Texas Instruments 功能描述: |
| 74F64LC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 74F64N | 制造商:NXP Semiconductors 功能描述: |
| 74F64PC | 功能描述:邏輯門 AND/OR Invert Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74F64SC | 功能描述:邏輯門 AND/OR Invert Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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