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參數(shù)資料
| 型號： | 74F595 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit shift register with output laches 3-State |
| 中文描述： | 8位的移位寄存器輸出懈怠三態(tài) |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 99K |
| 代理商： | 74F595 |
Philips Semiconductors
Product specification
74F595
8-bit shift register with output latches (3-State)
2
1990 Apr 18
853–1096 99392
FEATURES
Low noise, now switching feedthrough current
Controlled output edge rates
High impedance PNP base inputs for reduced loading
(20
μ
A in High and Low states)
8-bit serial-in, parallel-out shift register with storage
3-state outputs
Shift register has direct clear
Guaranteed shift frequency-DC to 100MHz
DESCRIPTION
The 74F595 contains an 8-bit serial-in, parallel-out shift register that
feeds an 8-bit D-type storage register. The storage register has
parallel 3-State outputs. Separate clocks are provided for both the
shift register and the storage register. The shift register has a direct
overriding clear, serial input and serial output pins for cascading.
Both the shift register and storage register clocks are positive
edge-triggered. If the user wishes to connect both clocks together,
the shift register state will always be one clock pulse ahead of the
storage register.
This device uses patented circuitry to control system noise and
internal ground bounce. This is done by eliminating switching
feedthrough current and controlling both Low-to-High and
High-to-Low slew rates.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Q7
V
CC
STCP
SHCP
SHR
OE
Q0
DS
Q1
Q2
Q6
Q3
Q4
Q5
SF01096
9
8
GND
QS
TYPE
TYPICAL f
MAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F595
130MHz
65mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
PKG DWG #
16-pin plastic DIP
N74F595N
SOT38-4
16-pin plastic SO
N74F595D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Ds
Serial data input
1.0/0.033
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
SHCP
Shift register clock pulse input (active rising edge)
1.0/0.033
STCP
Storage register clock pulse input (active rising edge)
1.0/0.033
SHR
Shift register reset input (active Low)
1.0/0.033
OE
Output Enable input (active Low)
1.0/0.033
Qs
Serial expansion output
50/33
1.0mA/20mA
Q0–Q7
Data outputs
150/40
3.0mA/24mA
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
相關(guān)PDF資料 |
PDF描述 |
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| 74F598 | 8-bit shift register with input storage registers(3-State)(帶輸入存儲寄存的8位移位寄存器（三態(tài)）) |
| 74F604 | Dual octal latch 3-State |
| 74F621 | Octal bus transceiver, non-inverting (open collector)(八通道總線收發(fā)器，同向（集電極開路）) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F595N | 制造商:NXP Semiconductors 功能描述: |
| 74F597 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit shift register with input storage registers |
| 74F598 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit shift register with input storage registers 3-State |
| 74F604 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual octal latch 3-State |
| 74F620 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Inverting Octal Bus Transceiver with 3-STATE Outputs |
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