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參數(shù)資料
| 型號： | 74F569SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Bidirectional Counter with 3-STATE Outputs |
| 中文描述： | F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO20 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-20 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 130K |
| 代理商： | 74F569SJ |
Philips Semiconductors
Product specification
74F569
4-bit bidirectional binary synchronous counter (3-State)
1996 Jan 05
9
AC WAVEFORMS (Continued)
For all waveforms, V
M
= 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
M
V
M
V
M
V
M
t
PLH
t
PHL
CET, SR, PE
TC, CC
SF01065
Waveform 3. Propagation Delays CET to TC
and SR or PE to CC
V
M
V
M
V
M
t
PLH
t
PHL
V
M
U/D
TC, CC
SF01066
Waveform 4. Propagation Delays U/D to TC and CC
t
PHL
V
M
V
M
SF01067
t
REC
Qn
t
W
(L)
CP
MR
Waveform 5. Master Reset Pulse Width, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
t
h
CP
V
M
V
M
V
M
V
M
V
M
V
M
t
s
t
s
(L)
t
s
(H)
t
h
= 0
D
n
PE
V
M
V
M
t
h
= 0
SF01068
DATA
STABLE
Waveform 6. Parallel Data and Parallel Enable Setup
and Hold Times
t
s
(L)
CP
Q
n
V
M
V
M
V
M
V
M
t
h
(L)
t
h
(H)
CET
CEP
t
s
(H)
NO
CHANGE
V
M
V
M
COUNT
V
M
V
M
NO CHANGE
SF01069
Waveform 7. Count Enable Data Setup and Hold Times
t
s
(L)
Q
n
CP
V
M
V
M
V
M
V
M
t
h
(L)
t
h
(H)
U/D
t
s
(H)
V
M
V
M
COUNT DOWN
COUNT UP
SF01070
Waveform 8. Up/Down Control Setup and Hold Times
t
s
(L)
CP
V
M
V
M
V
M
V
M
t
h
(L)
t
h
(H)
SR
t
s
(H)
V
M
V
M
SF01071
Waveform 9. Synchronous Reset Setup and Hold Times
V
M
V
M
V
M
t
PHZ
t
PZH
OE
Qn
V
OH
-0.3V
0V
SF01084
Waveform 10. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
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