參數(shù)資料
型號: 74F564
廠商: NXP Semiconductors N.V.
英文描述: Octal D flip-flop (3-State)(八D觸發(fā)器(三態(tài)))
中文描述: 八路D觸發(fā)器(3態(tài))(八?觸發(fā)器(三態(tài)))
文件頁數(shù): 5/10頁
文件大?。?/td> 80K
代理商: 74F564
Philips Semiconductors
Product specification
74F564
Octal D flip-flop (3-State)
1996 Jan 05
5
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITIONS
T
amb
= +25
°
C
V
= +5V
C
L
= 50pF, R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
= +5V
±
10%
C
L
= 50pF, R
L
= 500
MIN
UNIT
MAX
MAX
f
MAX
Maximum Clock frequency
Waveform
NO TAG
160
180
150
MHz
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
CP to Qn
Waveform
NO TAG
3.5
3.5
5.0
5.0
8.0
8.0
3.0
3.0
8.5
8.5
ns
Output Enable time
to High or Low level
Waveform 4
Waveform 5
2.5
4.0
4.5
5.5
7.5
8.0
2.0
3.5
8.0
8.5
ns
Output Disable time
from High or Low level
Waveform 4
Waveform 5
1.0
1.0
3.0
2.5
6.0
5.5
1.0
1.0
7.0
6.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITIONS
T
amb
= +25
°
C
V
= +5V
C
L
= 50pF, R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500
MIN
UNIT
MAX
MAX
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time,
Dn to CP
Waveform 3
2.0
2.0
2.0
2.5
ns
Hold time,
Dn to CP
Waveform 3
1.0
1.0
1.5
1.5
ns
CP pulse width,
High or Low
Waveform NO TAG
3.5
3.5
3.5
3.5
ns
AC WAVEFORMS
For all waveforms, V
M
= 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
t
W
(H)
t
PHL
CP
Qn
V
M
V
M
V
M
V
M
V
M
1/f
MAX
t
W
(L)
t
PLH
SF01051
Waveform 1. Propagation Delay, Clock and Enable Inputs
to Output, Enable, Clock Pulse Widths,
and Maximum Clock Frequency
V
M
V
M
V
M
t
PHL
Dn
Qn
V
M
t
PLH
SF00990
Waveform 2. Propagation Delay for Data to Outputs
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