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參數(shù)資料
| 型號： | 74F564 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal D flip-flop (3-State)(八D觸發(fā)器（三態(tài)）) |
| 中文描述： | 八路D觸發(fā)器（3態(tài)）（八?觸發(fā)器（三態(tài)）） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 80K |
| 代理商： | 74F564 |
Philips Semiconductors
Product specification
74F564
Octal D flip-flop (3-State)
2
1996 Jan 05
853-0166 16189
FEATURES
74F564 is broadside pinout version of 74F534
Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
Useful as an Input or Ouput port for Microprocessors
3-State Ouputs for Bus interfacing
Common Output Enable
74F574 is a non-inverting version of 74F564
DESCRIPTION
The 74F564 has a broadside pinout configuration to facilitate PC
board layout and allows easy interface with microprocessors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the register operation. When OE is Low, data in the
register appears at the outputs. When OE is High, the outputs are in
high impedance “off” state, which means they will neither drive nor
load the bus.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OE
GND
V
CC
CP
SF01052
Q0
D0
D1
Q1
D2
Q2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
TYPE
TYPICAL f
MAX
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F564
180MHz
50mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
PKG.
DWG #
20-Pin Plastic DIP
N74F564N
SOT146-1
20-Pin Plastic SOL
N74F564D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D7
Data inputs
1.0/1.0
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/0.6mA
OE
Output Enable input (active Low)
1.0/1.0
CP
Clock Pulse input (active rising edge)
1.0/1.0
Q0 - Q7
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
3-State outputs
150/40
3.0mA/24mA
LOGIC SYMBOL
3
4
5
6
7
8
14
15
16
17
18
19
1
11
CP
OE
Q0
D0
D1
Q1
D2
Q2
Q3
D3
Q4
D4
Q5
D5
9
2
12
13
Q6
D6
Q7
D7
SF01053
V
=Pin 20
GND=Pin 10
LOGIC SYMBOL (IEEE/IEC)
1
2D
EN1
1
SF01054
11
C2
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
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| 74F568SC | Synchronous Up/Down Counter |
| 74F569 | 4-bit bidirectional binary synchronous counter 3-State |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F564_00 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal D-Type Flip-Flop with 3-STATE Outputs |
| 74F564_TGH3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F564DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Octal D-Type Flip-Flop |
| 74F564PC | 功能描述:觸發(fā)器 Oct D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74F564SJ | 功能描述:觸發(fā)器 Oct D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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