參數(shù)資料
型號: 74AVCM162835DGG:11
廠商: NXP Semiconductors
文件頁數(shù): 8/10頁
文件大小: 0K
描述: IC RGSTRD DVR 3-ST 18BIT 56TSSOP
產(chǎn)品培訓模塊: Logic Packages
標準包裝: 2,000
系列: 74AVCM
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 1
每個元件的位元數(shù): 18
輸出電流高,低: 12mA,12mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74AVCM162835DG-T
74AVCM162835DG-T-ND
935264251118
Philips Semiconductors
Product specification
74AVCM162835
18-bit registered driver with 15
termination
resistors (3-State)
2001 Apr 20
7
AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V
RANGE
VM = 0.5 VCC
VX = VOL + 0.300 V
VY = VOH – 0.300 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND
VCC < 2.3 V RANGE
VM = 0.5 VCC
VX = VOL + 0.15 V
VY = VOH – 0.15 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI = VCC
An
INPUT
tPHL
tPLH
VOL
VI
GND
VOH
Yn
OUTPUT
SH00132
VM
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 1. Input (An) to output (Yn) propagation delay
LE INPUT
Yn OUTPUT
VI
GND
VOH
VOL
tPHL
tPLH
tW
SH00134
VM
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7V
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
CP INPUT
Yn OUTPUT
VI
GND
VOH
VOL
tPHL
tPLH
tW
1/fMAX
SH00135
VM
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 3. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
An
INPUT
LE
INPUT
tSU
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
tSU
th
VI
GND
VI
GND
SH00133
VM
VM = 0.5VCC at VCC = 2.3 to 2.7V
Waveform 4. Data set-up and hold times for the An input to the
LE input
VI
GND
An INPUT
VI
GND
VOH
Yn OUTPUT
VOL
CP INPUT
tsu
th
tsu
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SH00136
VM
VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
tPLZ
tPZL
VI
nOE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
tPHZ
VM
tPZH
VX
VY
SH00137
NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V
Waveform 6. 3-State enable and disable times
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