參數(shù)資料
型號: 74AVCM162835DGG:11
廠商: NXP Semiconductors
文件頁數(shù): 3/10頁
文件大?。?/td> 0K
描述: IC RGSTRD DVR 3-ST 18BIT 56TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,000
系列: 74AVCM
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 18
輸出電流高,低: 12mA,12mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74AVCM162835DG-T
74AVCM162835DG-T-ND
935264251118
Philips Semiconductors
Product specification
74AVCM162835
18-bit registered driver with 15
termination resistors
(3-State)
2
2001 Apr 20
853-2170 26096
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A/5/7.
CMOS low power consumption
Input/output tolerant up to 3.6 V
Low inductance multiple V
CC and GND pins for minimum noise
and ground bounce
Integrated 15 termination resistors to minimize output overshoot
and undershoot
Full PC133 solution provided when used with PCK2510S and
CBT16292
DESCRIPTION
The 74AVCM162835 is a 18-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor (Live
Insertion).
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
Y0
Y1
Y2
Y3
Y4
Y5
GND
VCC
GND
Y6
Y7
Y8
Y9
Y10
Y11
GND
Y12
Y13
Y14
VCC
Y15
Y16
GND
Y17
OE
LE
GND
NC
A0
GND
A1
A2
VCC
A3
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
A12
A13
A14
VCC
A15
A16
GND
A17
CP
GND
SH00130
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns; CL = 30 pF.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
2.6
2.0
1.7
ns
tPHL/tPLH
Propagation delay
LE to Yn;
CP to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
2.8
2.2
1.8
ns
CI
Input capacitance
5.0
pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
Outputs enabled
25
pF
CPD
Power dissi ation ca acitance er buffer
VI = GND to VCC1
Output disabled
6
F
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
ORDER CODE
DRAWING
NUMBER
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
–40 to +85
°C
74AVCM162835DGG
SOT364-1
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74AVCM162836 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-bit registered driver with inverted register enable and 15 ohm termination resistors 3-State
74AVCM162836DG 功能描述:總線收發(fā)器 20-BIT REG DRIVER W/15 TERM RE RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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