參數(shù)資料
型號(hào): 74AUP1G3208GM,132
廠商: NXP Semiconductors
文件頁數(shù): 19/19頁
文件大?。?/td> 0K
描述: IC 3-IN OR-AND GATE LP 6XSON
產(chǎn)品培訓(xùn)模塊: Logic Packages
特色產(chǎn)品: MicroPak?
標(biāo)準(zhǔn)包裝: 5,000
系列: 74AUP
邏輯類型: 與/或門
電路數(shù): 1
輸入數(shù): 3 輸入(2,1)
施密特觸發(fā)器輸入:
輸出類型: 單端
輸出電流高,低: 4mA,4mA
電源電壓: 0.8 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 6-XFDFN
供應(yīng)商設(shè)備封裝: 6-XSON,SOT886(1.45x1)
包裝: 帶卷 (TR)
其它名稱: 74AUP1G3208GM-H
74AUP1G3208GM-H-ND
935280617132
74AUP1G3208
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 22 June 2012
9 of 19
NXP Semiconductors
74AUP1G3208
Low-power 3-input OR-AND gate
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
All specified values are the average typical values over all stated loads.
[4]
CPD is used to determine the dynamic power dissipation (PD in
μW).
PD =CPD
× VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD
power dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
VCC = 0.8 V
-
2.6
-
pF
VCC = 1.1 V to 1.3 V
-
2.7
-
pF
VCC = 1.4 V to 1.6 V
-
2.8
-
pF
VCC = 1.65 V to 1.95 V
-
3.0
-
pF
VCC = 2.3 V to 2.7 V
-
3.5
-
pF
VCC = 3.0 V to 3.6 V
-
4.0
-
pF
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter
Conditions
25
°C
40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
(85
°C)
Max
(125
°C)
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
Input A, B and C to output Y propagation delay times
Y output
A, B, C input
Y output
GND
VI
VOH
VOL
VM
tPLH
tPHL
001aab593
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