參數(shù)資料
型號(hào): 74AUP1G3208GM,132
廠商: NXP Semiconductors
文件頁(yè)數(shù): 1/19頁(yè)
文件大小: 0K
描述: IC 3-IN OR-AND GATE LP 6XSON
產(chǎn)品培訓(xùn)模塊: Logic Packages
特色產(chǎn)品: MicroPak?
標(biāo)準(zhǔn)包裝: 5,000
系列: 74AUP
邏輯類(lèi)型: 與/或門(mén)
電路數(shù): 1
輸入數(shù): 3 輸入(2,1)
施密特觸發(fā)器輸入:
輸出類(lèi)型: 單端
輸出電流高,低: 4mA,4mA
電源電壓: 0.8 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 6-XFDFN
供應(yīng)商設(shè)備封裝: 6-XSON,SOT886(1.45x1)
包裝: 帶卷 (TR)
其它名稱(chēng): 74AUP1G3208GM-H
74AUP1G3208GM-H-ND
935280617132
1.
General description
The 74AUP1G3208 provides the Boolean function: Y = (A + B)
× C. The user can choose
the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2.
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9
μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 °Cto+85 °C and 40 °Cto+125 °C
74AUP1G3208
Low-power 3-input OR-AND gate
Rev. 5 — 22 June 2012
Product data sheet
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