參數(shù)資料
型號(hào): 74ALVCH16543DGG,11
廠商: NXP Semiconductors
文件頁(yè)數(shù): 14/20頁(yè)
文件大?。?/td> 0K
描述: IC TRANSCVR TRI-ST 16BIT 56SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,000
系列: 74ALVCH
邏輯類型: 寄存收發(fā)器,非反相
元件數(shù): 2
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 24mA,24mA
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74ALVCH16543DG-T
74ALVCH16543DG-T-ND
935262544118
1999 Nov 23
3
Philips Semiconductors
Product specication
16-bit D-type registered transceiver; 3-state
74ALVCH16543
QUICK REFERENCE DATA
Ground = 0; Tamb =25 °C; tr =tf = 2.5 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
CL = output load capacitance in pF;
fo = output frequency in MHz;
VCC = supply voltage in Volts;
Σ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PINNING
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay nAn,nBn to nBn,nAn
CL = 50 pF;
VCC = 3.3 V
3.8
ns
CI
input capacitance
4.0
pF
CPD
power dissipation capacitance per latch
notes 1 and 2
outputs enabled
44
pF
outputs disabled
14
pF
OUTSIDE NORTH
AMERICA
NORTH
AMERICA
PACKAGE
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74ALVCH16543DGG
ACH16543 DGG
40 to +85 °C
56
TSSOP
plastic
SOT364-1
PIN
SYMBOL
DESCRIPTION
1 and 28
1OEAB, 2OEAB
output enable A-to-B for register 1 or 2
2 and 27
1LEAB, 2LEAB
latch enable A-to-B for register 1 or 2
3 and 26
1EAB, 2EAB
A-to-B enable for register 1 or 2
4, 11, 18, 25, 32, 39, 46 and 53
GND
ground (0 V)
5, 6, 8, 9, 10, 12, 13 and 14
1A0 to 1A7
data inputs/outputs
7, 22, 35 and 50
VCC
DC supply voltage
15, 16, 17, 19, 20, 21, 23 and 24
2A0 to 2A7
data inputs/outputs
29 and 56
2OEBA, 1OEBA
output enable B-to-A for register 1 or 2
30 and 55
2LEBA, 1LEAB
latch enable B-to-A for register 1 or 2
31 and 54
2EBA, 1EBA
B-to-A enable for register 1 or 2
33, 34, 36, 37, 38, 40, 41 and 42
2B7 to 2B0
data inputs/outputs
43, 44, 45, 47, 48, 49, 51 and 52
1B7 to 1B0
data inputs/outputs
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