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參數(shù)資料
| 型號： | 74ALVCH16543DGG,11 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSCVR TRI-ST 16BIT 56SSOP |
| 產(chǎn)品培訓模塊： | Logic Packages |
| 標準包裝： | 2,000 |
| 系列： | 74ALVCH |
| 邏輯類型： | 寄存收發(fā)器，非反相 |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 8 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 1.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74ALVCH16543DG-T 74ALVCH16543DG-T-ND 935262544118 |
1999 Nov 23
2
Philips Semiconductors
Product specication
16-bit D-type registered transceiver; 3-state
74ALVCH16543
FEATURES
In accordance with JEDEC standard no 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE flow-through pin-out architecture
16-bit transceiver with D-type latch
Combines 16245 and 16373 type functions in one chip
Back-to-back registers for storage
Output drive capability 50 transmission lines at 85 °C
Separate controls for data flow in each direction
All data inputs have bus hold
3-state non-inverting outputs for bus oriented
applications
Current drive ±24 mA at 3.0 V.
DESCRIPTION
The 74ALVCH16543 is a dual octal registered transceiver.
Each section contains two sets of D-type latches for
temporary storage of the data flow in either direction.
Separate latch enable (nLEAB, nLEBA) and output enable
(nOEAB, nOEBA) inputs are provided for each register to
permit independent control in either direction of the data
flow.
The ‘16543’ contains two sections each consisting of two
sets of eight D-type latches with separate inputs and
controls for each set. For data flow from A to B, for
example, the A-to-B enable (nEAB, where n equals 1 or 2)
inputs must be LOW in order to enter data from nA0 to nA7,
or take data from nB0 to nB7, as indicated in the function
table. With nEAB LOW, a LOW signal on the A-to-B latch
enable (nLEAB) input makes the A-to-B latches
transparent; a subsequent LOW-to-HIGH transition of the
nLEAB signal stores the A data into the latches. With nEAB
and nOEAB both LOW, the 3-state B output buffers are
active and display the data present at the output of the
A latches. Similarly, the nEBA, nLEBA and nOEBA signals
control the data flow from B-to-A.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
FUNCTION TABLE
See note 1.
Note
1. XX = AB for A-to-B direction, BA for B-to-A direction;
H = HIGH voltage level; L = LOW voltage level;
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of nLEAB,nLEBA,nEAB or nEBA;
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or nEBA;
X = don’t care; NC = no change;
↑ = LOW-to-HIGH level transition;
Z = high-impedance OFF-state.
INPUTS
OUTPUTS
STATUS
nOEXX
nEXX
nLEXX
nBn,nAn
H
X
Z
disabled
X
H
X
Z
disabled
L
↑
L
h
Z
disabled and latch
L
↑
Ll
Z
LL
↑
h
H
latch and display
LL
↑
lL
L
H
transparent
LLLL
L
H
X
NC
hold
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