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參數(shù)資料
| 型號(hào)： | 74ALVC162835T |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26з Series Resistors in Outputs |
| 中文描述： | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 89K |
| 代理商： | 74ALVC162835T |
2002 Fairchild Semiconductor Corporation
DS500646
www.fairchildsemi.com
September 2001
Revised February 2002
7
R
74ALVC162835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs/Outputs
and 26
Series Resistors in Outputs
General Description
The ALVC162835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
n
) to Outputs (O
n
) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The ALVC162835 is designed with 26
series resistors in
the outputs. This design reduces noise in applications such
as memory address drivers, clock drivers, and bus trans-
ceivers/transmitters.
The 74ALVC162835 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC162835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
Compatible with PC100 DIMM module specifications
I
1.65V to 3.6V V
CC
specifications provided
I
3.6V tolerant inputs and outputs
I
26
series resistors in outputs
I
t
PD
(CLK to O
n
)
5.4 ns max for 3.0V to 3.6V V
CC
6.3 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Supports live insertion/withdrawal (Note 1)
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high impedance state during power up or power
down, OE should be tied to V
CC
through a pulldown resistor; the minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package
Number
MTD56
Package Description
74ALVC162835T
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVC162835TX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Buffer/Driver |
| 74ALVC162836A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State |
| 74ALVC162836A_0006 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State |
| 74ALVC162836ADG | 功能描述:總線收發(fā)器 20-BIT REG DRVR W/INV REG RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVC162836ADGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State |
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