參數(shù)資料
型號(hào): 74ABT
廠商: National Semiconductor Corporation
英文描述: Octal Transparent Latch with TRI-STATE Outputs
中文描述: 八路透明鎖存器與三態(tài)輸出
文件頁(yè)數(shù): 2/16頁(yè)
文件大?。?/td> 338K
代理商: 74ABT
Functional Description
The
’ABT373
contains
TRI-STATE output buffers. When the Latch Enable (LE) in-
put is HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
in the bi-state mode. When OE is HIGH the buffers are in
the high impedance mode but this does not interfere with
entering new data into the latches.
eight
D-type
latches
with
Truth Table
Inputs
Output
LE
OE
D
n
O
n
H
H
L
X
L
L
L
H
H
L
X
X
H
L
O
n
(no change)
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance State
Logic Diagram
TL/F/11547–3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
相關(guān)PDF資料
PDF描述
74ABT373CDCQB Octal Transparent Latch with TRI-STATE Outputs
74ABT373CDCX Octal Transparent Latch with TRI-STATE Outputs
74ABT373CDMQB Octal Transparent Latch with TRI-STATE Outputs
74ABT373CDMX Octal Transparent Latch with TRI-STATE Outputs
74ABT373CFCQB Octal Transparent Latch with TRI-STATE Outputs
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