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參數(shù)資料
| 型號(hào)： | 74ABT373CDMQB |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Octal Transparent Latch with TRI-STATE Outputs |
| 中文描述： | 八路透明鎖存器與三態(tài)輸出 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大?。?/td> | 338K |
| 代理商： | 74ABT373CDMQB |
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TL/F/11547
5
September 1995
54ABT/74ABT373
Octal Transparent Latch with TRI-STATE
é
Outputs
General Description
The ’ABT373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
Features
Y
TRI-STATE outputs for bus interfacing
Y
Output sink capability of 64 mA, source capability of
32 mA
Y
Guaranteed output skew
Y
Guaranteed multiple output switching specifications
Y
Output switching specified for both 50 pF and 250 pF
loads
Y
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Y
Guaranteed latchup protection
Y
High impedance glitch free bus loading during entire
power up and power down
Y
Nondestructive hot insertion capability
Y
Standard Military Drawing (SMD) 5962-9321801
Commercial
Military
Package
Number
Package Description
74ABT373CSC (Note 1)
M20B
20-Lead (0.300
×
Wide) Molded Small Outline, JEDEC
20-Lead (0.300
×
Wide) Molded Small Outline, EIAJ
20-Lead (0.300
×
Wide) Molded Dual-In-Line
74ABT373CSJ (Note 1)
M20D
74ABT373CPC
N20B
54ABT373J/883
J20A
20-Lead Ceramic Dual-In-Line
74ABT373CMSA (Note 1)
MSA20
20-Lead Molded Shrink Small Outline, EIAJ Type II
54ABT373W/883
W20A
20-Lead Cerpack
54ABT373E/883
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
74ABT373CMTC (Notes 1, 2)
MTC20
20-Lead Molded Thin Shrink Small Outline, JEDEC
Note 1:
Devices also available in 13
×
reel. Use suffix
e
SCX, SJX, MSAX, and MTCX.
Note 2:
Contact factory for package availability.
Connection Diagrams
Pin Assignment
for DIP, SOIC, SSOP and Flatpak
TL/F/11547–1
Pin Assignment
for LCC
TL/F/11547–2
Pin Names
Description
D
0
–D
7
LE
Data Inputs
Latch Enable Input
(Active HIGH)
Output Enable Input
(Active LOW)
TRI-STATE Latch
Outputs
OE
O
0
–O
7
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ABT373CDMX | Octal Transparent Latch with TRI-STATE Outputs |
| 74ABT373CFCQB | Octal Transparent Latch with TRI-STATE Outputs |
| 74ABT373CFCX | Octal Transparent Latch with TRI-STATE Outputs |
| 74ABT373CFMQB | Octal Transparent Latch with TRI-STATE Outputs |
| 74ABT373CFMX | Octal Transparent Latch with TRI-STATE Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ABT373CDMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transparent Latch with TRI-STATE Outputs |
| 74ABT373CFCQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transparent Latch with TRI-STATE Outputs |
| 74ABT373CFCX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transparent Latch with TRI-STATE Outputs |
| 74ABT373CFMQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transparent Latch with TRI-STATE Outputs |
| 74ABT373CFMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transparent Latch with TRI-STATE Outputs |
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