參數(shù)資料
型號(hào): 74ABT651DB
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Octal transceiver/register, inverting 3-State
中文描述: ABT SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24
封裝: PLASTIC, SSOP-24
文件頁(yè)數(shù): 3/7頁(yè)
文件大?。?/td> 88K
代理商: 74ABT651DB
Philips Semiconductors
Product specification
74ABT651
Octal transceiver/register, inverting (3-State)
1995 Sep 06
3
FUNCTION TABLE
INPUTS
CPAB
H or L
H or L
X
X
X
H or L
DATA I/O
OPERATING MODE
OEAB
L
L
X
H
L
L
L
L
H
H
OEBA
H
H
H
H
X
L
L
L
H
H
CPBA
H or L
H or L
X
H or L
X
X
SAB
X
X
X
**
X
X
X
X
L
H
SBA
X
X
X
X
X
**
L
H
X
X
An
Bn
Input
Input
Isolation
Store A and B data
Store A, Hold B
Store A in both registers
Hold A, Store B
Store B in both registers
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Store A data to B bus
Stored A data to B bus
Stored B data to A bus
Input
Unspecified
output*
Unspecified
output*
Input
Output
Input
Input
Output
H
L
H or L
H or L
H
H
Output
Output
H =
L
X =
=
*
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be
staggered in order to load both registers.
=
**
LOGIC DIAGRAM
1D
C1
Q
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
5
6
7
8
9
10
11
A1
A2
A3
A4
A5
A6
A7
DETAIL A X 7
OEBA
OEAB
CPBA
SBA
CPAB
SAB
21
3
23
22
1
2
20
B0
1D
C1
Q
4
A0
1of 8 Channels
SA00098
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