參數(shù)資料
型號(hào): 74ABT544PW,118
廠商: NXP Semiconductors
文件頁(yè)數(shù): 16/16頁(yè)
文件大小: 0K
描述: IC TRANSCVR 3ST 8BIT INV 24TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: 74ABT
邏輯類(lèi)型: 收發(fā)器,反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 32mA,64mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74ABT544PW-T
74ABT544PW-T-ND
935178850118
74ABT544
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 3 November 2011
9 of 16
NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; 3-state
VM =1.5 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9.
Data set-up and hold times and latch enable pulse width
001aae905
VM
An, Bn
LEAB, LEBA,
EAB, EBA
VM
tsu(H)
th(H)
tsu(L)
th(L)
tWL
VI
GND
VI
GND
a. Input pulse definition
b. Test circuit
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 10. Load circuitry for switching times
001aai298
VM
tW
10 %
90 %
0 V
VI
negative
pulse
positive
pulse
0 V
VM
90 %
10 %
90 %
10 %
tf
tr
tf
VEXT
VCC
VI
VO
mna616
DUT
CL
RT
RL
G
Table 8.
Test data
Input
Load
VEXT
VI
fI
tW
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
3.0 V
1 MHz
500 ns
2.5 ns
50 pF
500
open
7.0 V
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