參數(shù)資料
型號(hào): 74ABT544PW,118
廠商: NXP Semiconductors
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 0K
描述: IC TRANSCVR 3ST 8BIT INV 24TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: 74ABT
邏輯類型: 收發(fā)器,反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 32mA,64mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74ABT544PW-T
74ABT544PW-T-ND
935178850118
1.
General description
The 74ABT544 high performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT544 octal latched transceiver contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate latch enable (LEAB, LEBA) and output
enable (OEAB, OEBA) inputs are provided for each register to permit independent control
of data transfer in either direction. The outputs are guaranteed to sink 64 mA.
2.
Features and benefits
Combines 74ABT640 and 74ABT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Live insertion and extraction permitted
Output capability: +64 mA to
32 mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3.
Ordering information
74ABT544
Octal latched transceiver with dual enable; 3-state
Rev. 6 — 3 November 2011
Product data sheet
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74ABT544D
40 Cto+85 C
SO24
plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
74ABT544DB
40 Cto+85 C
SSOP24
plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74ABT544PW
40 Cto+85 C
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
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