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參數(shù)資料
| 型號： | 74ABT16500C |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 18-bit universal bus transceiver 3-State |
| 中文描述： | 18位通用總線收發(fā)器，三態(tài) |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 88K |
| 代理商： | 74ABT16500C |
Philips Semiconductors
Product specification
74ABT16500C
74ABTH16500C
18-bit universal bus transceiver (3-State)
1998 Feb 27
4
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
OEAB
A-to-B Output enable input
27
OEBA
B-to-A Output enable input (active low)
2, 28
LEAB/LEBA
A-to-B/B-to-A Latch enable input
55,30
CPAB/CPBA
A-to-B/B-to-A Clock input (active falling edge)
3, 5, 6, 8, 9, 10, 12, 13, 14, 15,
16, 17, 19, 20, 21, 23, 24, 26
A0-A17
Data inputs/outputs (A side)
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
B0-B17
Data inputs/outputs (B side)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
Internal
Registers
OUTPUTS
OPERATING MODE
OEAB
LEAB
CPAB
An
Bn
L
H
X
X
X
Z
Disabled
L
↓
X
h
H
Z
Disabled Latch data
Disabled, Latch data
L
↓
X
I
L
Z
L
L
H or L
X
NC
Z
Disabled, Hold data
L
L
↓
h
H
Z
Disabled Clock data
Disabled, Clock data
L
L
↓
I
L
Z
H
H
X
H
H
H
Transparent
H
H
X
L
L
L
H
↓
X
h
H
H
Latch data & display
H
↓
X
I
L
L
H
L
↓
h
H
H
Clock data & display
H
L
↓
I
L
L
H
L
H or L
X
H
H
Hold data & display
H
L
H or L
X
L
L
NOTE:
A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level
h
= High voltage level one set-up time prior to the Enable or Clock transition
L
= Low voltage level
I
= Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don’t care
Z = High Impedance “off” state
↓
= High-to-Low Enable or Clock transition
相關PDF資料 |
PDF描述 |
|---|---|
| 74ABT16500CDGG | 18-bit universal bus transceiver 3-State |
| 74ABT16500CDL | 18-bit universal bus transceiver 3-State |
| 74ABTH16500C | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-SOIC 0 to 70 |
| 74ABTH16500CDGG | 18-bit universal bus transceiver 3-State |
| 74ABTH16500CDL | 18-bit universal bus transceiver 3-State |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74ABT16500CDGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit universal bus transceiver 3-State |
| 74ABT16500CDL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit universal bus transceiver 3-State |
| 74ABT16500CDL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| 74ABT16500CMTD | 功能描述:總線收發(fā)器 18-Bit Reg Bus Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ABT16500CMTD_Q | 功能描述:總線收發(fā)器 18-Bit Reg Bus Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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